CCSDS AR4JA LDPC

Benefits High throughput design. Frame-to-frame on-the-fly configuration. Configurable LDPC decoding iterations allows trading-off throughput and error correction performance. Features The AR4JA LDPC code family is

802.11 LDPC

Benefits High throughput design. Frame-to-frame on-the-fly configuration. Configurable LDPC decoding iterations allows trading-off throughput and error correction performance. Features Throughput matching the required specifications. Bit-error-rate

Viterbi Decoder

System Overview Convolutional FEC codes are very popular because of their powerful error correction capability and are especially suited for correcting random errors. The most

Flash Memory LDPC

Features Quasi cyclic (QC) – Algebraic constructed – LDPC code Regular parity check matrix Codeword length: 16 K Code rate: 0.953 No or very low

DVB-C2 LDPC Decoder

Features Irregular parity check matrix Layered Decoding Minimum sum algorithm Configurable number of iterations Soft decision decoding ETSI EN 302 769 V1.3.1 (2015-10) compliant Functional

DVB-T2-LDPC-BCH

Features Irregular parity check matrix Layered decoding Minimum sum algorithm Soft decision decoding BCH decoder corrects up to t errors where t = 10 or

DVB-S2-LDPC-BCH

Features Irregular parity check matrix Layered decoding Minimum sum algorithm Soft decision decoding BCH decoder works on GF (2m) where m=16 or 14 and corrects

DVB-S2X-LDPC Decoder

Features Irregular parity check matrix coding Layered Decoding Minimum sum algorithm Soft decision decoding ETSI EN 302 307-2 V1.1.1 compliant Long, medium, and short codeword

DVB-S2 LDPC Decoder

Features Irregular parity check matrix Layered Decoding Minimum sum algorithm Configurable number of iteration Soft decision decoding ETSI EN 302 307-1 V1.4.1 compliant Functional Description

DVB-T2/Lite LDPC Decoder

Features Irregular parity check matrix Layered Decoding Minimum sum algorithm Configurable number of iteration Soft decision decoding ETSI EN 302 755 V1.4.1 (2015-07) compliant T2-Lite