Nonbinary LDPC Decoder

Benefits

  •  Low area design. 
  •  Low-power and low-complexity design. 
  •  Regular parity check matrix. 
  •  Configurable number of decoding iterations. 
  •  Soft decision SPA decoding. 
  •  Hard decision output. 
  •  Higher order Galois field GF(2m).

Features

  • Throughput matching the required specifications. 
  • Bit-error-rate and block-error-rate performance meet the required specifications. 
  • Compliant with BeiDou Navigation Satellite. 
  • Supports different code sizes 
  • Log domain implementation.

Functional Description

  • A powerful Forward Error Correction (FEC) subsystem is needed in almost all wireless communication systems. Low-Density Parity-Check (LDPC) codes are a powerful family of FEC codes that allow for very low error-rates, approaching the Shannon capacity limit.
  • While binary LDPC codes have shown great performance, nonbinary LDPC codes have empirically shown even better performance, especially for small codeword lengths.
  • A configurable output synchronous FIFO is used to store the output for the next block.

IP Deliverables

  •  Synthesizable Verilog
  •  System Model (Matlab)
  •  Verilog Test Benches
  •  Documentation

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